1. Field of the Invention
The present invention relates to a method for erasing data from a non-volatile semiconductor memory device. More particularly, the present invention relates to a method for erasing data from a non-volatile semiconductor memory device which employs a write method using channel hot electrons. 2. Description of the Related Art
An ETOX (registered trademark of Intel; EPROM Thin Oxide) type non-volatile semiconductor memory device is the most widely used conventional non-volatile semiconductor memory device (a flash memory). Japanese Patent Publication for Opposition No. 6-82841 (Conventional Example 1) discloses a non-volatile semiconductor memory device of this type. Referring to FIG. 1, the structure of a cell of an ETOX type non-volatile semiconductor memory device will be described. The non-volatile semiconductor memory device cell includes a source 14a and a drain 14b which are formed on a substrate 10, with a channel layer 14c extending therebetween. A floating gate 16 is provided over the channel layer 14a via a tunnel oxide film 15. Moreover, a control gate 18 is provided over the floating gate 16 via an interlayer insulating film 17.
The principle of operation of an ETOX type non-volatile semiconductor memory device will now be described. Table 1 shows voltages to be respectively applied to the control gate 18, the drain 14b, the source 14a and the substrate 10 in a write mode, an erase mode, and a read mode.
In the write (programming) mode, a voltage of 10 V, for example, is applied to the control gate 18 of the memory cell to which data is to be written, a reference voltage of 0 V, for example, is applied to the source 14a thereof, and a voltage of 6 V, for example, is applied to the drain 14b. A large current of 500 xcexcA/cell flows through the channel region 14c, thereby generating channel hot electrons (hereinafter, referred to as xe2x80x9cCHEsxe2x80x9d) in a portion of the drain 14b side of the memory cell where there is a high electric field. Basically, CHEs are high-energy electrons which are generated by a high electric field and which flow through the channel. When CHEs jump over the energy barrier of the tunnel oxide film so as to be injected into the floating gate 16, the threshold voltage of the memory cell increases. The drain of each memory cell (non-selected memory cell) to which no data is to be written is set to a reference voltage (e.g., 0 V). The memory cell to which data has been written as described above has a threshold voltage equal to or greater than 5.5 V as shown in FIG. 2 by the curve labelled xe2x80x9cProgrammed state (a)xe2x80x9d. As shown in FIG. 2, each memory cell whose threshold voltage is equal to or less than 3.5 V is in an erased state, and each memory cell whose threshold voltage is equal to or greater than 5.5 V is in a written (programmed) state.
In the erase mode, a voltage of xe2x88x929 V, for example, is applied to the control gate 18 and a voltage of 6 V, for example, is applied to the source 14a, whereby electrons are withdrawn from the floating gate 16 on the source 14a side of the memory cell, thereby reducing the threshold voltage. In such a case, the memory cell has a threshold voltage as shown in FIG. 2 by the curve labelled xe2x80x9cErased state (b)xe2x80x9d. Thus, the threshold voltage of the memory cell whose data has been erased is less than or equal to 3.5 V.
FIG. 3 illustrates how electrons are withdrawn from the source side. In the erase operation, a BTBT (band to band tunneling) current flows through the device, as shown in FIG. 3. Simultaneously with this current flow, hot holes and hot electrons are generated. While the hot electrons flow into the substrate, the hot holes are drawn toward the tunnel oxide film and trapped therein. It is believed in the art that this trapping degrades the reliability of the device.
For a memory cell to/from which data has been written/erased, a read operation can be performed by applying a voltage of 5 V to the control gate 18 and a voltage of 1 V to the drain 14b, while controlling the potential of the source 14a to be 0 V. Under such voltage conditions, if data stored in the memory cell is in the erased state, the threshold voltage of the memory cell is less than or equal to 3.5 V. Therefore, a current flows through the memory cell, which is detected by a sense circuit (not shown) connected to the drain, whereby the data in the memory cell is determined to be xe2x80x9c1xe2x80x9d (i.e., in the erased state). If data stored in the memory cell is in the written state, the threshold voltage of the memory cell is equal to or greater than 5.5 V, and no current flows through the memory cell, whereby the data in the memory cell is determined by the sense circuit to be xe2x80x9c0xe2x80x9d (i.e., in the written state).
The write, erase and read operations are performed according to such a principle of operation. In an actual device, the erase operation is performed in a relatively larger unit of blocks, e.g., by 64-kB blocks. Within each block to be erased, the memory cells have varied threshold voltages because some of the memory cells have data in the programmed state and other memory cells have data in the erased state. Therefore, it is necessary to perform the erase operation by using a complicated algorithm as shown in FIG. 4 (Japanese Laid-Open Publication No. 9-320282).
The erase method shown in FIG. 4 will now be described. When the erase operation is initiated, all of the memory cells in one block are brought into a written state by an ordinary write operation (the write method using CHEs) (step S1).
Next, a program verify operation is performed by 8-bit blocks (step S2) for verifying that the threshold voltage of the memory cell to which data has been written in step S1 is equal to or greater than 5.5 V. If the threshold voltage of the memory cell is not equal to or greater than 5.5 V, the process returns to step S1 to continue the write operation. If the threshold voltage is equal to or greater than 5.5 V, the process proceeds to step S3.
In step S3, an erase pulse is applied to the memory cells by blocks. Data is erased from a memory cell by withdrawing electrons from the source side of the memory cell so as to reduce the threshold voltage thereof. Next, in step S4, an erase verify operation is performed for verifying that the threshold voltage of each of the memory cells in the block is less than or equal to 3.5 V. If the threshold voltage of the memory cell is not less than or equal to 3.5 V, the process returns to step S3 to continue the erase operation. If the threshold voltage of the memory cell is less than or equal to 3.5 V, the erase operation is completed.
As can be seen, in the erase method of FIG. 4, all of the memory cells in a block to be erased are first brought to a written state so that the threshold voltage distribution after the erase operation is as narrow as possible and that there are no over-erased cells (i.e., a cell whose threshold voltage is less than or equal to 0 V). This write operation can be performed for eight memory cells at once by an ordinary program operation. If the write time for one memory cell is 2 xcexcs, the amount of time required for this write operation (or the pre-erase write time) is obtained as follows:
2 xcexcsxc3x9764 kB/8=131 ms
If the total erase time is 600 ms, the pre-erase write time accounts for about 20% of the total erase time. The pre-erase write time of 131 ms holds in the case where a 5 V power source is used, and increases to 262 ms in the case where a 3 V power source is used. This is because when a 3 V power source is used, the capability of the charge pump for increasing the supply voltage to obtain the pre-erase write voltage, e.g., the voltage applied to the control gate, is poor, so that the pre-erase write operation can be performed for only 4 bits at a time, thereby resulting in the increase in the pre-erase write time. The problem of the long pre-erase write time is more pronounced as the level of the supply voltage is reduced.
The program verify operation in step S2 is performed by 8-bit blocks with a verification time per one cell of 100 ns. Thus, the amount of time required for the program verify operation is about 6.6 ms (=100 nsxc3x9764 kB/8).
Moreover, the current consumption is large because the verify operation is performed by 8-bit blocks. Furthermore, the application of the erase pulse in step S3, if performed by a conventional method, may cause a BTBT current as described above. As a result, a relatively large current flows through the device. The total time required for applying the erase pulse is about 300 ms, and the current consumption therefor is about 5.24 mA where the current consumption per one cell is 10 nA and each block includes 64 kB cells (10 nAxc3x9764 kB).
Since the write operation is performed by using CHEs, the peak value of the write current per one cell is 500 xcexcA. Thus, a very large current is consumed.
In the erase method of FIG. 4, the total pulse application time may be reduced by increasing the voltage to be applied to the source in the erase pulse application operation. However, if the source voltage is increased, the BTBT current also increases, thereby increasing the holes which are trapped in the tunnel oxide film, and degrading the reliability of the device. Thus, it is not possible to further increase the source voltage and therefore, it is not possible to further increase the erase speed.
As described above, problems associated with conventional ETOX type flash memories include the following: (1) the erase speed is low; and (2) the current consumption is large. Problem (1) occurs since the programming of all of the bits in a block before the erase pulse application (i.e., the pre-erase write operation) takes a long time, whereby it is not possible to reduce the amount of time required for the erase pulse application. Problem (2) occurs as follows. The current consumption is large because the pre-erase write operation (the operation of writing all of the bits in a block before the erase pulse application) uses CHEs. The current consumption is further increased because the BTBT current flows through the device in the erase pulse application operation. In addition, a large current is also consumed in the verify operation which is performed after the pre-erase write operation.
One solution to the above-described problems is the method disclosed in Japanese Laid-Open Publication No. 6-96592 (Conventional Example 2). According to this method, the pre-erase write operation is performed on all of the memory cells at once through a Fowler-Nordheim (or xe2x80x9cFNxe2x80x9d) tunnel phenomenon. The memory cells which can be used with this method are the same as those shown in FIG. 1. Table 2 shows voltages to be respectively applied to the control gate 18, the drain 14b, the source 14a and the substrate 10 in a write mode, an erase mode, a pre-erase write mode, and a read mode.
As can be seen from Table 2, a high voltage (18 V) is applied to the control gate in the pre-erase write operation. Therefore, a high electric field is generated between the channel region of the memory cell and the floating gate, whereby electrons are injected from the channel region of the memory cell into the floating gate. In this method, the amount of current to be consumed per one cell is as small as 10 pA because the method utilizes the FN tunnel phenomenon in the pre-erase write operation. Therefore, it is possible to simultaneously write data to a plurality of memory cells in one block, and to reduce the amount of time required for the pre-erase write operation, even when considering the capability of the charge pump and the value of acceptable current of the lines used in the IC.
However, the method of Conventional Example 2 has the following problems. Since the voltage to be applied to the word line which is connected to the control gate is as high as 18 V, it is necessary to use highly voltage resistant transistors in the word line output stage. Therefore, the area to be occupied by the transistors increases, thereby increasing the layout area of the device. Such a voltage value of 18 V is higher than normal operation voltages which are used in practice. This in turn complicates the structure of booster charge pumps to be provided in the device for generating such a high voltage, increasing the area to be occupied by such booster charge pumps, and thus increasing the layout area of the device. Moreover, the use of a high voltage may increase the stress on transistors in peripheral circuits, thereby degrading the reliability of the device.
According to one aspect of this invention, there is provided a method for erasing data from a non-volatile semiconductor memory device including a plurality of memory cells arranged in a matrix in which data can be electrically written to or erased from each of the memory cells, each of the memory cells being formed by a field effect transistor including a drain, a source, a floating gate and a control gate, the plurality of memory cells being grouped into one or more blocks, each of the blocks including a first well of a first conductivity type which is provided on a substrate of a second conductivity type, a second well of the second conductivity type which is provided on the first well so as to be electrically isolated from the substrate by the first well, and a plurality of memory cells having a plurality of sources which are provided on the second well, the sources of the memory cells in each block being commonly connected to one another. The method includes the steps of: withdrawing electrons from each floating gate of each of the memory cells through a Fowler-Nordheim tunnel phenomenon so as to perform a batch erase operation of erasing data from all of the memory cells in each block; and prior to the batch erase operation, performing a pre-erase write operation in which a first voltage, a second voltage of an opposite polarity to the first voltage and a third voltage of the same polarity as the first voltage are respectively applied to the control gates, the second wells and the first wells of all of the memory cells in the block to be erased so that electrons are injected into the floating gates of each of the memory cells through a Fowler-Nordheim tunnel phenomenon.
In one embodiment of the invention, first voltage and the third voltage are positive voltages, the second voltage is a negative voltage, and the first voltage is higher than the third voltage.
In one embodiment of the invention, in the batch erase operation, a negative voltage is applied to each control gate of each of the memory cells and a positive voltage is applied to each source of the memory cells so as to withdraw electrons from a source side of the memory cells, thereby reducing a threshold voltage of the memory cells.
In one embodiment of the invention, in the batch erase operation, a negative voltage is applied to each control gate of each of the memory cells, and a positive voltage is applied to each source of each of the memory cells and the second well so as to withdraw electrons from a channel region between respective sources and drains, thereby reducing a threshold voltage of the memory cells.
In one embodiment of the invention, in the pre-erase write operation, a positive voltage is applied to each control gate of each of the memory cells, and a negative voltage is applied to each source of each of the memory cells and the second well so that electrons are injected from a channel region between respective sources and drains into the floating gate, thereby increasing a threshold voltage of the memory cells.
Thus, the invention described herein makes possible the advantages of providing a method for erasing data from a non-volatile semiconductor memory device in which it is possible to reduce a voltage to be applied to a control gate in a pre-erase write operation.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.